The present invention is directed generally to thermal control of a device under test (DUT) and specifically to thermal control of a DUT using a thermal control wafer or chip having a plurality of independent thermal elements.
Generally, electrical and burn-in testing is frequently carried out on diced packaged or unpackaged semiconductor chips. Tustaniwskyj, et al., U.S. Pat. Nos. 5,821,505 and 5,844,208 describe a procedure to estimate the temperature of diced semiconductor chips based on the measured temperatures of a heat sink and an electric heater interposed between the chip and the heat sink. The estimated temperature is then used to control the heater power and temperature to maintain the chip at a desired temperature during testing.
As semiconductor devices get smaller and the pressure to cut semiconductor processing and testing costs and time has grown, two trends have emerged. The first trend is the increased power dissipation, and hence self-heating of semiconductor devices. A second trend is a drive toward performing device burn-in and electrical testing at the wafer level before the wafer is cut into individual device chips to decrease testing time and cost. However, prior thermal control systems generally do not provide a sufficient amount of temperature control for wafers and high power dissipation chips undergoing electrical and burn-in testing.
One preferred aspect of the present invention provides a solid state thermal control device, comprising a substrate, and a plurality of solid state thermal elements on the substrate adapted to provide thermal control to a device under test (DUT). Each solid state thermal element comprises at least one solid state heater and a control circuit adapted to control a thermal output of the solid state heater.
Another preferred aspect of the present invention provides a solid state thermal control device, comprising a plurality of first means for providing thermal control to a device under test (DUT) undergoing burn-in or electrical testing, a plurality of second means for providing control of a magnitude of a thermal output of the plurality of first means, and a third means for supporting the plurality of the first means and the second means.
Another preferred aspect of the present invention provides a semiconductor wafer testing system, comprising a thermal control wafer which comprises a semiconductor wafer substrate and a plurality of solid state thermal elements on the substrate adapted to provide thermal control to a wafer under test (WUT). Each thermal element comprises at least one solid state heater and a control circuit adapted to control a thermal output of the solid state heater. The system also comprises an electrical testing or burn-in processing probe located opposite a first side of the thermal control wafer, such that a wafer under test (WUT) location opening is created between the thermal control wafer and the probe, and a thermal reservoir located in thermal contact with a second side of the thermal control wafer.
Another preferred aspect of the present invention provides a method of testing a DUT, comprising placing a first side of a DUT in thermal contact with a thermal control substrate containing a plurality of solid state thermal elements, placing an electrical testing probe in contact with a second surface of the DUT, performing electrical testing or burn-in processing of the DUT, wherein the DUT in an unheated state has at least one of a non-uniform spatial and temporal temperature or power dissipation during the testing, and heating the DUT using the solid state thermal elements such that the DUT has a substantially uniform respective spatial, temporal or spatial and temporal temperature profile during testing.